the information provided herein is believed to be reliable at press time. sirenza microdevices assumes no responsibility for ina ccuracies or ommisions. sirenza microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at th e user?s own risk. prices and specifications are subject to change without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. sirenza microdevices does not authorize or warrant any sirenza microdevices product for use in life-support devices and/or systems. copyright 2002 sirenza microdevices, inc. all worldwide rights reserved. 303 south technology court broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 1 eds-103535 rev f preliminary sirenza microdevices? SZA-6044 is a high linearity class a gaas heterojunction bipolar transistor (hbt) amplifier housed in a low-cost surface-mountable plastic package. these hbt amplifiers are fabricated using molecular beam epitaxial growth technology which produces reliable and consistent performance from wafer to wafer and lot to lot. this product is specifically designed as a driver or final stage amplifier for equipment in the 5.1 - 5.9 ghz band. it can run from a 3v to 5v supply. load line optimization for target band is possible outside the package. its high lin- earity makes it an ideal choice for multicarrier and digital applications. key specifications symbol parameters: test conditions, with app circuit z 0 = 50 w , v cc = 5.0v, i = 165ma, t bp = 30oc) unit min. typ. max. f o frequency of operation mhz 5100 5900 p 1db output power at 1db compression ? 5.1 ghz dbm 24.9 output power at 1db compression ? 5.5 ghz 24.6 output power at 1db compression ? 5.9 ghz 22.5 24.0 26.0 s 21 small signal gain ? 5.1 ghz db 17.0 18.5 20.0 small signal gain ? 5.5 ghz 17.3 small signal gain ? 5.9 ghz 14.9 16.4 17.9 irl worst case input return loss 5.1-5.9ghz db 8 11 orl worst case output return loss 5.1-5.9ghz db 12 17 oip 3 output ip3, pout per tone = +8dbm @ 5.9 ghz dbm 37 39 pout 802.11a 54mb/s pout @ 3% evm @ 5.9ghz, i = 165ma dbm 17 nf noise figure @ 5.9 ghz db 7.8 9.8 i supply total device current, i vbias + i ctotal = 150ma i vpc12 = 15ma ma 145 165 185 r th, j-l thermal resistance (junction - lead) oc/w 56 functional block diagram SZA-6044 5.1 ? 5.9 ghz ? watt power amplifier with active bias product features applications ? single 3v to 5v operation ? high linearity class a oip3 = 39dbm @ 5v ? 802.11a 54mb/s pout = 17dbm @ 3% evm ? p1db 24dbm @ 5v, 21dbm @ 3.3v ? surface mount plastic package ? power up/down control < 1 m s ? ofdm ? multicarrier applications ? 802.11a wlan driver stage ? fixed wireless, unii product description 4mm x 4mm qfn package vc1 vpc2 nc nc nc nc vbias nc vpc1 rfin rfout nc nc rfout rfout rfin nc nc nc nc 1 2 3 4 5 6 7 9 8 10 11 12 13 14 15 16 17 18 19 20 active bias
303 south technology court broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 2 eds-103535 rev f preliminary SZA-6044 5.1-5.9 ghz ? w amplifier pin out description pin # function description 1,2,5,6, 7,8,9,10, 11,15,16 n/c pins are not used. may be grounded, left open or connected to adjacent pin. 19 vpc2 vpc2 is the bias control pin for the stage 2 active bias circuit. an external series resistor is required for proper setting of bias levels. refer to the evaluation board schematic for resistor value. 20 vpc1 vpc1 is the control pin for the stage 1 active bias circuits. an external series resistor is required for proper set- ting of bias levels. refer to the evaluation board schematic for resistor value. 18 vbias vbias is the active bias circuit supply voltage. can be operated from 3v to 5v. 3,4 rfin rf input pin. this is dc grounded internal to the ic. do not apply voltage to this pin. both pins 3 and 4 must be used for proper operation. 12,13,14 rfout/ vc2 rf output and second stage collector supply voltage pin. vc2 in the range of 3v to 5v voltage should be sup- plied to this pin through an external rf choke. because dc biasing is present on this pin, a dc blocking capacitor should be used in most applications (see evaluation board schematic). the supply side of the bias network should be well bypassed. the output network and board layout specified in the app circuit is recom- mended for optimum performance. all pins 12-14 are required to be wired together at lead foot for proper operation. 17 vc1 vc1 is the first stage collector supply voltage. can be operated over the range of 3v to 5v. epad gnd exposed area on the bottom side of the package needs to be soldered to the ground plane of the board for optimum thermal and rf performance. several vias should be located under the epad as shown in the rec- ommended land pattern (page 5). caution: esd sensitive - class 1b appropriate precaution in handling, packaging and testing devices must be observed. absolute maximum ratings parameters value unit 1st stage collector bias current (i vc1 ) 100 ma 2nd stage collector bias current (i vc2 ) 190 ma device voltage (v d ) 6.0 v power dissipation 1.5 w operating lead temperature (t l ) -40 to +85 oc rf input power 20 dbm storage temperature range -40 to +150 oc operating junction temperature (t j ) +150 oc esd human body model - class 1b 500 v operation of this device beyond any one of these limits may cause permanent damage. for reliable continuous operation the device voltage and current must not exceed the maximum operating values specified in the table on page one. bias conditions should also satisfy the following expression: i d v d < (t j - t l ) / r th? j-l simplified device schematic 3 4 active bias 20 17 active bias 19 18 12 13 14 vc1 q1 q2 1 2 5 6 7 8 n/c vpc1 rf in vpc2 rf out/ vc2 vbias 9 10 11 15 16
303 south technology court broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 3 eds-103535 rev f preliminary SZA-6044 5.1-5.9 ghz ? w amplifier 5.1 - 5.9 ghz evaluation board data (v bias = 5.0v, i bias = 165ma) input/output return loss, isolation vs frequency +25c -45 -40 -35 -30 -25 -20 -15 -10 5100 5200 5300 5400 5500 5600 5700 5800 5900 frequency(mhz) return loss (db) s12 s22 s11 device current vs source voltage 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0 1 2 3 4 5 6 vcc(v) device current(a) +25c -40c +85c gain vs temp 12 13 14 15 16 17 18 19 20 21 22 5100 5200 5300 5400 5500 5600 5700 5800 5900 frequency(mhz) gain (db) +25c -40c +85c output thrid order intercept vs frequency (pout/tone = 2dbm) 32.0 33.0 34.0 35.0 36.0 37.0 38.0 39.0 40.0 41.0 42.0 5100 5200 5300 5400 5500 5600 5700 5800 5900 frequency (mhz) oip3 (dbm) +25c -40c +85c broadband gain, input/output return loss vs frequency +25c -35 -25 -15 -5 5 15 25 1 2 3 4 5 6 frequency (ghz) db s11 s21 s22 p1db vs frequency 23.0 23.3 23.5 23.8 24.0 24.3 24.5 24.8 25.0 25.3 25.5 25.8 26.0 5100 5300 5500 5700 5900 frequency (mhz) p1 (dbm) +25c -40c +85c
303 south technology court broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 4 eds-103535 rev f preliminary SZA-6044 5.1-5.9 ghz ? w amplifier 802.11a 64qam 54mb/s error vector magnitude data (v bias = 5.0v, i bias = 165ma) evm burst average% vs output power (dbm) freq = 5.35ghz 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 2 4 6 8 10 12 14 16 18 20 output power (dbm) bavg% +25c -40c +85c evm burst average% vs output power (dbm) freq = 5.725ghz 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 2 4 6 8 10 12 14 16 18 20 output power (dbm) bavg% +25c -40c +85c evm burst average% vs output power (dbm) freq = 5.875ghz 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 2 4 6 8 10 12 14 16 18 20 output power (dbm) bavg% +25c -40c +85c evm burst average% vs output power (dbm) freq = 5.15ghz 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 2 4 6 8 10 12 14 16 18 20 output power (dbm) bavg% +25c -40c +85c
303 south technology court broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 5 eds-103535 rev f preliminary SZA-6044 5.1-5.9 ghz ? w amplifier 5.1 - 5.9 ghz evaluation board schematic for 5v supply rf input internally ground. use dc block if exteral dc voltage is present. v 8 zo=50 ,54.2 @ 5.5ghz ,22.3 zo=29 v @ 5.5ghz 8 ,38.4 zo=29 v @ 5.5ghz 8 ,16 zo=13 v @ 5.5ghz 8 c5 c1 c4 c2 q1 l1 r2 r1 c3 5.1 - 5.9 ghz evaluation board layout for 5v - board material getek, 31mil thick, dk=3.9, 2 oz. copper note: for 3.3v 140ma operation, lower v+ to 3.3v and change r1 and r2 to 50 ohm. rf performance at 3.3v, 140ma: gain increases 0.5db, ip3 drops ~ 3db and p1db drops ~3db relative to 5v data. return loss is essentially unchanged relative to 5v data. contact factory for more details.
303 south technology court broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com 6 eds-103535 rev f preliminary SZA-6044 5.1-5.9 ghz ? w amplifier package outline drawing part number ordering information part number reel size devices/reel SZA-6044 13? 3000 part symbolization the part will be symbolized with an ?SZA-6044? mark- ing designator on the top surface of the package. recommended land pattern (dimensions in mm[in]): recommended pcb soldermask (smboc) for land pattern (dimensions in mm[in]): 1.58 [0.062] 0.50 [0.020] 0.26 [0.010] 0.38 [0.015] 0.29 [0.011] 0.21 [0.008] 1.58 [0.062] 0.75 [0.030] ?0.38 [?0.015] 0.005 chamfer (8pl) plated thru (4pl)
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